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STYLOS SYS Team

Jurij Pfeifer
industrial and grafic design

Janez Poženel
acoustic research

Igor Jež
tecnical ingenir

info@stylos-sys.com
The entire HAD electronics excluding the part for power supply is set in the Inox housing and filled with a special epoxy compound that nullifies the unwanted frequencies, which are not a part of the algorithm.

The algorithm of HAD is based on the last generation of the 24 bit/192kHz Sampling, Advanced Segment converter, produced by Texas Instruments. The converter is uniquely connected into the audio logarithm as a result of long-lasting researches of the STYLOS SYS development team in the field of digital technology and its deficiencies. Although these converters are 24-bit converters, they have proved themselves in the given algorithm with the best sound results, when working with a 16 bit resolution and the system clock set to 384 Fs. The algorithm uses also a digital filter with 8x oversampling because the popular "zero oversampling" has proved itself entirely inappropriate as far as the sound is concerned. Had does not use any processor or operational amplifier in its electronics since both of them turned out to be inappropriate for audio purpose.

I/V converter and the output stage with the 1. order filter, both extra developed for the HAD's algorithm, are the result of the proficiency of the STYLOS SYS development team. The output stage is set to the A class and "single ended" structure, without any return connection, neither negative nor positive. In the output stage and the I/V converter the IRF MOS-FET transistors are used, proving to be more appropriate because of their neutral sound, compared to the electron tubes whose specific character is mostly impossible to get rid of, however, the topology can be the same in both cases. The output stage has no trouble with impedance matching because it can work until the short circuit and that gives it the output impedance of 0 virtual Ohms. The output stage is balanced. Balanced outlets enable the maximum dynamics of the component. Balanced (XLR) signal is twice as strong as the signal of the SE (RCA) outlets.

The charging of HAD is carried out in Semi regulated MOS-FET power supply circuit for analog filter stage, the I/V conversion and the analog output stage, as well as separated charging for digital and analog parts of the conversion algorithm. All the electronics' components are electronic industrial elements of high quality and low tolerance, assuring a durable functioning of the component.

There are analog outlets built in the back sub-plate, engraved with a laser; some of them are XLR balanced outlets, others RCA outlets. Digital inputs are the 75-ohm RCA input and the BNC input. We recommend you to use the BNC input because of a lower "jitter". Digital inputs accept all the PCM coded signals according to the S/PDIF and AES3id standards. The AES/EBU digital input standard is not used because of the capacity problems of the pairs of long digital shielded cables. The BNC digital input is also recommended for long digital connectors because at the input of HAD's electronics every digital signal gets stronger. Only one of the digital inputs can be connected at a time.

Stylos Sys HAD DAC Specifications

Digital input:

Single BNC (75 Ohm) and RCA connector (S/PDIF, AES3id standard digital audio interface)
1.2V p-p 1.6mA max. input; 10m (S/PDIF), 1000m (AES3id) max. distance of coax. cable
Up to 48kHz accepted sampling frequeny, up to 16bit accepted wordlength

Analog output:

Disktere MOS-SET class A, no feedback, servoless, DC coupled, short circuit proofed
symmetrical output stage
XLR balanced output ( 5V RMS at 0 dB )
RCA SE output ( 2,5V RMS at 0 dB )
Virtually 0 Ohm output impendance
Linearity +/- 0.5 dB ( 20Hz - 20kHz )

Power supply:

Internal no switching power supply
110/120 (on request) or 220/230V AC (on request) 50/60Hz input voltage

Semi regulated MOS FET power supply circuit for analog stage
Full regulated power supply for DAC alghrithm
3 separate high quality UI transformers

Mesurments and other specification:

Total harmonic distortion plus nois:
Smaller than 0.1% ( Fs=44.1kHz at 0dB )

Dynamic range:
117dB ( EIAJ, A-weighted, Fs=44.1kHz )

Signal-to-noise ration:
117dB ( EIAJ, A-weightet, Fs=44.1kHz )

Channel separation:
115dB ( Fs=44.1kHz )

24bit/192kHz Texsas Instruments DAC
8x oversampling digital filter
Low-jitter clock recovery
384 Fs system clock frequency
Jitter attenution down to subsonic frequencies
No processor or mute electronic is used in conversion algorithm

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